1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of fabricating the same. More particularly, the present invention relates to a nonvolatile semiconductor memory device and a method of fabricating the same that can improve electrical characteristics and a degree of integration of a floating gate tunneling oxide (FLOTOX) type and an electrically erasable programmable read only memory (EEPROM) type semiconductor memory device.
2. Description of the Related Art
In general, an electrically erasable programmable read only memory (EEPROM) cell includes a floating gate that is electrically insulated with a periphery like in an erasable programmable read only memory (EPROM). An EEPROM records data of “1” or “0” by injecting or discharging electrons into/from the floating gate. However, the EEPROM utilizes an electron injecting/discharging mechanism that is very different from that of the EPROM.
In the EPROM, the injection of electrons into the floating gate is performed by a hot electron having a higher energy than the electrons flowing between a source and a drain, and the discharge of electrons is performed by an energy of ultraviolet light. On the contrary, in the EEPROM, the injection and discharge of the electrons into/from the floating gate are performed by a tunnel current that passes through a tunnel insulating layer having a thickness of about 100 Å. That is, even though the tunnel insulating layer is an insulator, e.g., SiO2, if a high electric field, e.g., higher than 10 MeV/cm, is applied to both ends of the tunnel insulating layer, a Fowler-Nordheim (F-N) current flows. Thus, the injection and discharge of the electrons in the EEPROM is performed using the F-N current.
Primarily, a floating gate tunneling oxide (FLOTOX) type EEPROM cell and a metal nitride oxide semiconductor (MNOS) type EEPROM cell are used in semiconductor devices. The FLOTOX memory cell used as a standard memory cell includes two transistors, i.e., a selection transistor that selects a desired bit line and a memory transistor that stores data as one memory cell. In the memory transistor, a floating gate for storing data by accumulated electric charges and a control gate for controlling the floating gate are formed while interposing a thin interlayer dielectric therebetween.
FIG. 1 illustrates a cross-sectional view of a nonvolatile semiconductor memory device including a conventional FLOTOX memory cell.
Referring to FIG. 1, a selection transistor 5 and a memory transistor 7 are separated from each other by a predetermined distance. More specifically, a first conductive layer 31 formed of a polysilicon, an interlayer dielectric 32, and a second conductive layer 33 formed of a polysilicon are formed as gate patterns 30 of the selection transistor 5 and the memory transistor 7 on an upper portion of a gate oxide layer 12 surrounding a tunnel insulating layer 14 on a surface of a semiconductor substrate 10. A source region 20 of the memory transistor 7 and a bit line junction region 24 of the selection transistor 5 are located in the semiconductor substrate 10. A cell doping region 26, in which n-type impurities are doped in high concentration, is located on a lower portion of the tunnel insulating layer 14 for facilitating performance of the injection and discharge of electrons. A high concentration doping region 26′ for reducing a contact resistance may be further formed on a side surface of the cell doping region 26 in a direction of the selection transistor 5.
A width L1 and a thickness of the tunnel insulating layer 14 are very important in a reliability of the EEPROM. In particular, because the width L1 of the tunnel insulating layer 14 is directly related to the integrity of the EEPROM, it is desirable that the width L1 is narrow.
FIG. 2 illustrates a cross-sectional view of an area “a” shown in FIG. 1 for illustrating problems in the conventional EEPROM.
Referring to FIG. 2, a first depletion region 28 is generated on a boundary of the cell doping region 26, when a voltage is applied to the bit line junction region 24. More specifically, both sides and the lower end of the cell doping region 26, and portions contacting the tunnel insulating layer 14 and the gate insulating layer 12 are depleted, as shown by a second depletion region 29. The width of the first depletion region 28 increases as the applied voltage increases. The increase of the width causes a band-to-band tunneling phenomenon by connecting the first and second depletion regions 28 and 29. When the band-to-band tunneling phenomenon occurs, current is leaked in the first and second depletion regions 28 and 29 due to electron-hole pairs.
In FIG. 2, a distance D1 between end portions of the tunnel insulating layer 14 and the cell doping region 26 can be increased so that the first and second depletion regions 28 and 29 do not contact each other, however, as the distance D1 increases, the integrity of the EEPROM is reduced. Therefore, it is desirable that the distance D1 is short. Consequently, the distance D1 and the width L1 of the tunnel insulating layer 14 should be minimized in order to increase the integrity of the EEPROM without allowing contact between the first and second depletion regions 28 and 29.
However, the tunnel insulating layer 14 is generally formed by wet etching a thermal oxide layer (not shown) to expose the substrate 10, and thermally oxidizing the exposed substrate 10. Since the wet etching method is an isotropic etching method, the etching is performed in a direction of the side surface of the substrate, thus the width L1 of the tunnel insulating layer 14 may become larger than the desired pattern size. In addition, the etching time increases and the etching is made along an interface between a photoresist pattern (not shown) and the thermal oxide layer. Accordingly, a profile of the sidewall of the tunnel insulating layer 14 becomes inclined. The inclined profile degrades an efficiency of the EEPROM programming similar to the increase of the width L1 of the tunnel insulating layer 14.